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Circuit Sage Tools | Submit a tool Weak Inversion Design
Calculates 3 sigma mismatch between two arrays of identical MOS devices (same size, orientation and environment) and expresses mismatch in three different forms: referred to the gates (e.g. in a differential pair in delta Vgs ), referred to the drain (percentage of output current difference), and as DNL in a current DAC when changing DAC code input from p to q assuming p and q devices are identical but distinct. DNL is expressed as a percentage of the current in one single transistor. Note that all the formulas assume that all layout used best practice, as referred to in literature. Transistor Parameters from Inversion Coefficient
This tool calculates Vgs and Vdsat for all inversion regions from weak to moderate to strong of a MOS device. The substrate back biasing is also taken into account (Vs is defined with respect to bulk voltage). These formulas give a good fit with the simulator outputs across the whole range of inversion coefficients.. Inversion Coefficient Calculator
This tool calculates the inversion coefficient based on its geometry (W/L ratio) and it bias current. First Previous 1 Next Last
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