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This course covers the circuit and system design of equalized high-speed I/Os. Today's high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints, and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient and the power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital communications, optimization, statistical, and dynamic system modeling with system architecture, mixed-signal, and digital circuit design. This course will lay the groundwork for this type of system-driven I/O design by covering each of the required layers in link system hierarchy.